Feasible delay Bound Definition

Abstract : Minimizing the number of iterations when satisfying performance constraints in IC design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
Complete list of metadatas

Cited literature [18 references]  Display  Hide  Download

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239363
Contributor : Nadine Azemard <>
Submitted on : Wednesday, September 11, 2019 - 4:03:26 PM
Last modification on : Wednesday, September 11, 2019 - 4:04:09 PM

File

Feasible_Delay_Bound_Definitio...
Publisher files allowed on an open archive

Identifiers

Citation

Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002, IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩. ⟨lirmm-00239363⟩

Share

Metrics

Record views

115

Files downloads

16