Feasible delay Bound Definition

Abstract : Minimizing the number of iterations when satisfying performance constraints in IC design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
Type de document :
Chapitre d'ouvrage
SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239363
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 15:47:22
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00239363, version 1

Citation

Michel Aline, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, Kluwer Academic Publishers, pp.325-335, 2002. 〈lirmm-00239363〉

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