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Formal Sizing Rules of CMOS Circuits

Daniel Auvergne 1 Nadine Azemard 2, * Vincent Bonzom 1 Denis Deschacht 2 Michel Robert 2 
* Corresponding author
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.
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Submitted on : Saturday, March 19, 2022 - 10:43:43 AM
Last modification on : Friday, August 5, 2022 - 10:48:24 AM
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Daniel Auvergne, Nadine Azemard, Vincent Bonzom, Denis Deschacht, Michel Robert. Formal Sizing Rules of CMOS Circuits. EDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩. ⟨lirmm-00239374⟩



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