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Conference Papers Year : 1998

Path Selection for Delay and Power Performance Optimization

Abstract

Based on an incremental path search algorithm, this paper addresses the problem of path selection for delay and power performance optimization. Delay and power/area constraints are managed through circuit path sizing alternatives defined with a realistic evaluation of gate delays. Demonstration of this technique is given through examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
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Dates and versions

lirmm-00239415 , version 1 (05-02-2008)

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  • HAL Id : lirmm-00239415 , version 1

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Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection for Delay and Power Performance Optimization. SAME: Sophia Antipolis Forum on Microelectronics, Oct 1998, Sophia Antipolis, France. pp.48-53. ⟨lirmm-00239415⟩
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