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Path Selection for Delay and Power Performance Optimization

Abstract : Based on an incremental path search algorithm, this paper addresses the problem of path selection for delay and power performance optimization. Delay and power/area constraints are managed through circuit path sizing alternatives defined with a realistic evaluation of gate delays. Demonstration of this technique is given through examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
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Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Tuesday, February 5, 2008 - 4:44:23 PM
Last modification on : Monday, October 11, 2021 - 1:24:09 PM


  • HAL Id : lirmm-00239415, version 1


Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection for Delay and Power Performance Optimization. SAME: Sophia Antipolis Forum on Microelectronics, Oct 1998, Sophia Antipolis, France. pp.48-53. ⟨lirmm-00239415⟩



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