Path Selection for Delay and Power Performance Optimization

Abstract : Based on an incremental path search algorithm, this paper addresses the problem of path selection for delay and power performance optimization. Delay and power/area constraints are managed through circuit path sizing alternatives defined with a realistic evaluation of gate delays. Demonstration of this technique is given through examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
Type de document :
Communication dans un congrès
SAME'98 : Sophia Antipolis Forum on Microelectronics, Sophia Antipolis, Nice, France, pp.48-53, 1998
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239415
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 16:44:23
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00239415, version 1

Citation

Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection for Delay and Power Performance Optimization. SAME'98 : Sophia Antipolis Forum on Microelectronics, Sophia Antipolis, Nice, France, pp.48-53, 1998. 〈lirmm-00239415〉

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