Path Selection for Delay and Power Performance Optimization

Abstract : Based on an incremental path search algorithm, this paper addresses the problem of path selection for delay and power performance optimization. Delay and power/area constraints are managed through circuit path sizing alternatives defined with a realistic evaluation of gate delays. Demonstration of this technique is given through examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239415
Contributor : Nadine Azemard <>
Submitted on : Tuesday, February 5, 2008 - 4:44:23 PM
Last modification on : Tuesday, October 23, 2018 - 2:48:03 PM

Identifiers

  • HAL Id : lirmm-00239415, version 1

Citation

Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Selection for Delay and Power Performance Optimization. SAME'98 : Sophia Antipolis Forum on Microelectronics, Sophia Antipolis, Nice, France, pp.48-53. ⟨lirmm-00239415⟩

Share

Metrics

Record views

90