Delay-Power Performance Analysis - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 1999

Delay-Power Performance Analysis

Abstract

Based on an incremental path search algorithm, this paper addresses the problem of low power performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Demonstration of this technique is given on examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from EPIC tool and SPICE used as a reference.
No file

Dates and versions

lirmm-00239424 , version 1 (05-02-2008)

Identifiers

Cite

Séverine Cremoux, Michel Aline, Nadine Azemard, Daniel Auvergne. Delay-Power Performance Analysis. ICECS: International Conference on Electronics, Circuits and Systems, Sep 1999, Pafos, Cyprus. pp.1543-1546, ⟨10.1109/ICECS.1999.814465⟩. ⟨lirmm-00239424⟩
62 View
0 Download

Altmetric

Share

Gmail Facebook X LinkedIn More