High performance of fast VLSI design with gate array based approaches implies realistic consideration of physical constraints such as layout, wiring, delay and power. This paper adresses the problem of post layout iterative gate sizing process under delay and power performance constraints. Circuit path sizing procedure is defined with a realistic evaluation of gate delay and power and an accurate estimation of parasitic capacitances. This sizing protocol is detailed for delay or power optimization, or delay/power trade-off and demonstrated on ISCAS'85 benchmarks . Implemented in POPS (Performance Optimization by Path selection), the accuracy of this sizing heuristic is compared to an industrial optimization tool, AMPS from Synopsis society.