Performance Indicators for Designing CMOS Logic

Abstract : The fast evolution of CMOS processes makes mandatory the use of metrics for performance as easy and robust indicators to evaluate the different alternatives at all the steps of the design flow. In this paper we present performance indicators used as well to evaluate the performances of CMOS design than to predict their evolution during process migration. These indicators are defined for process speed characterization, cell efficiency in terms of load and duration time of input controlling signals and for supply voltage sensitivity. Examples of validation are given for different processes ranging from 1.2 to 0.18μm
Keywords : CMOS logic circuits
Complete list of metadatas

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239446
Contributor : Nadine Azemard <>
Submitted on : Tuesday, February 5, 2008 - 5:25:16 PM
Last modification on : Friday, September 13, 2019 - 10:19:39 AM

Identifiers

Citation

Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Indicators for Designing CMOS Logic. ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩. ⟨lirmm-00239446⟩

Share

Metrics

Record views

87