Performance Indicators for Designing CMOS Logic

Abstract : The fast evolution of CMOS processes makes mandatory the use of metrics for performance as easy and robust indicators to evaluate the different alternatives at all the steps of the design flow. In this paper we present performance indicators used as well to evaluate the performances of CMOS design than to predict their evolution during process migration. These indicators are defined for process speed characterization, cell efficiency in terms of load and duration time of input controlling signals and for supply voltage sensitivity. Examples of validation are given for different processes ranging from 1.2 to 0.18μm
Type de document :
Communication dans un congrès
ICM'01: 13th International Conference on Microelectronic, Oct 2001, Rabat, Maroc, pp.125-129, 2001
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239446
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 17:25:16
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00239446, version 1

Citation

Philippe Maurine, Nadine Azemard, Daniel Auvergne. Performance Indicators for Designing CMOS Logic. ICM'01: 13th International Conference on Microelectronic, Oct 2001, Rabat, Maroc, pp.125-129, 2001. 〈lirmm-00239446〉

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