Timing Closure Management based on Delay Bound Determination

Abstract : In this paper we present a method to determine the feasibility of delay constraint imposed on circuit path. This is of prime importance in minimizing the number of iterations when satisfying performance constraints in IC design. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
Type de document :
Communication dans un congrès
VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.430-434, 2001
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239452
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 17:36:55
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00239452, version 1

Citation

Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Timing Closure Management based on Delay Bound Determination. VLSI-SoC'01: 11th IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference, Dec 2001, Montpellier, France, pp.430-434, 2001. 〈lirmm-00239452〉

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