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Timing Closure Management based on Delay Bound Determination

Abstract : In this paper we present a method to determine the feasibility of delay constraint imposed on circuit path. This is of prime importance in minimizing the number of iterations when satisfying performance constraints in IC design. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
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Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Tuesday, February 5, 2008 - 5:36:55 PM
Last modification on : Friday, August 5, 2022 - 10:48:20 AM


  • HAL Id : lirmm-00239452, version 1


Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Timing Closure Management based on Delay Bound Determination. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434. ⟨lirmm-00239452⟩



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