Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures

Abstract : For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows up the design and load parameters. Validations are performed on different configurations of inverters by comparison with HSPICE simulations. Discussions on the relative importance of short-circuit and dynamic power dissipation is given, together with considerations allowing an easy extension to gates.
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Sandra Turgis, Nadine Azemard, Daniel Auvergne. Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures. ISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩. ⟨lirmm-00241153⟩

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