Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241153
Contributor : Nadine Azemard <>
Submitted on : Wednesday, February 6, 2008 - 10:35:43 AM
Last modification on : Tuesday, October 23, 2018 - 2:48:03 PM

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Sandra Turgis, Nadine Azemard, Daniel Auvergne. Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures. ISLPD'95: International Symposium on Low Power Design, Apr 1995, Dana Point Resort, CA, USA, pp.129-134. ⟨lirmm-00241153⟩

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