Path Resizing Based on Incremental Technique

Abstract : Based on an incremental path search algorithm, this paper addresses the problem of longest combinational paths selection for performance optimization at physical level. A realistic evaluation of gate delay and controlled sizing techniques are used to manage the circuit path sizing alternatives, such as delay or power/area constraints. The efficiency of this technique is demonstrated and also illustrated on several ISCAS'85 benchmark circuits. A comparison is given between regular sizing alternatives to local optimization steps controlled by specific indicators.
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Communication dans un congrès
ISCAS'98: IEEE International Symposium on Circuits and Systems, May 1998, Monterey, CA, USA, pp.71, 1998
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241190
Contributeur : Nadine Azemard <>
Soumis le : mercredi 6 février 2008 - 10:50:35
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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  • HAL Id : lirmm-00241190, version 1

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Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Path Resizing Based on Incremental Technique. ISCAS'98: IEEE International Symposium on Circuits and Systems, May 1998, Monterey, CA, USA, pp.71, 1998. 〈lirmm-00241190〉

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