Delay Bound Determination for Path Constraint Satisfaction

Abstract : This paper addresses the problem of path constraint satisfaction from delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factor and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.
Type de document :
Communication dans un congrès
ISMA'00: International Symposium on Microelectronics and Assembly, MSO4 : Design, Modeling and Simulation, Nov 2000, Singapour, pp.122 - 129, 2000
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241266
Contributeur : Nadine Azemard <>
Soumis le : mercredi 6 février 2008 - 11:02:10
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

Identifiants

  • HAL Id : lirmm-00241266, version 1

Collections

Citation

Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Path Constraint Satisfaction. ISMA'00: International Symposium on Microelectronics and Assembly, MSO4 : Design, Modeling and Simulation, Nov 2000, Singapour, pp.122 - 129, 2000. 〈lirmm-00241266〉

Partager

Métriques

Consultations de la notice

46