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Delay Bound Determination for Path Constraint Satisfaction

Abstract : This paper addresses the problem of path constraint satisfaction from delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factor and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241266
Contributor : Nadine Azemard <>
Submitted on : Wednesday, February 6, 2008 - 11:02:10 AM
Last modification on : Wednesday, September 11, 2019 - 3:16:01 PM

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Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Path Constraint Satisfaction. ISMA: International Symposium on Microelectronics and Assembly, Nov 2000, Singapour, China. pp.122-129, ⟨10.1117/12.405403⟩. ⟨lirmm-00241266⟩

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