Delay Bound Determination for Path Constraint Satisfaction - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Communication Dans Un Congrès Année : 2000

Delay Bound Determination for Path Constraint Satisfaction

Résumé

This paper addresses the problem of path constraint satisfaction from delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factor and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.
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Dates et versions

lirmm-00241266 , version 1 (06-02-2008)

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Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Path Constraint Satisfaction. ISMA: International Symposium on Microelectronics and Assembly, Nov 2000, Singapour, China. pp.122-129, ⟨10.1117/12.405403⟩. ⟨lirmm-00241266⟩
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