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Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241327
Contributor : Nadine Azemard <>
Submitted on : Wednesday, February 6, 2008 - 11:13:11 AM
Last modification on : Thursday, September 12, 2019 - 9:14:10 PM

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  • HAL Id : lirmm-00241327, version 1

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Nadine Azemard, Denis Deschacht, Michel Robert, Daniel Auvergne. Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108. ⟨lirmm-00241327⟩

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