Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 1992
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lirmm-00241327 , version 1 (06-02-2008)

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  • HAL Id : lirmm-00241327 , version 1

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Nadine Azemard, Denis Deschacht, Michel Robert, Daniel Auvergne. Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108. ⟨lirmm-00241327⟩
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