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Design and Sizing of Tapered Buffers for Minimum Power-Delay Product

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241366
Contributor : Nadine Azemard <>
Submitted on : Wednesday, February 6, 2008 - 11:37:25 AM
Last modification on : Thursday, September 12, 2019 - 9:09:05 PM

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  • HAL Id : lirmm-00241366, version 1

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Sandra Turgis, Nadine Azemard, Daniel Auvergne. Design and Sizing of Tapered Buffers for Minimum Power-Delay Product. PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.79-90. ⟨lirmm-00241366⟩

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