Selective Gate Sizing for Delay/Power Performance Management - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 1997
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lirmm-00241374 , version 1 (06-02-2008)

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  • HAL Id : lirmm-00241374 , version 1

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Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Selective Gate Sizing for Delay/Power Performance Management. IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France. ⟨lirmm-00241374⟩
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