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Selective Gate Sizing for Delay/Power Performance Management

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241374
Contributor : Nadine Azemard <>
Submitted on : Wednesday, February 6, 2008 - 11:49:26 AM
Last modification on : Thursday, September 5, 2019 - 7:03:51 PM

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  • HAL Id : lirmm-00241374, version 1

Citation

Séverine Cremoux, Nadine Azemard, Daniel Auvergne. Selective Gate Sizing for Delay/Power Performance Management. IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France. ⟨lirmm-00241374⟩

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