A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2008

A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Abstract

Aggressive scaling of transistors is often accompanied by an increase in variability of its intrinsic parameters. In this paper, we point out the importance of considering sensitivity performances due to process variations during SRAM design. We propose a novel dummy bitline driver, an essential component in a self timed merory, which is less sensitive to process variations. A statistical sizing method of this dummy bitline driver is introduced so as to improve the read timing margin, while ensuring a high timing yield. The memory considered is a 253kb SRAM design in 90nm technology node.
Fichier principal
Vignette du fichier
min2008.pdf (630.62 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

lirmm-00243966 , version 1 (27-06-2022)

Identifiers

Cite

Michael Yap San Min, Philippe Maurine, Magali Bastian Hage-Hassan, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA 2008 - 4th IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.107-110, ⟨10.1109/DELTA.2008.72⟩. ⟨lirmm-00243966⟩
169 View
34 Download

Altmetric

Share

More