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Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244002
Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Thursday, February 7, 2008 - 10:58:37 AM
Last modification on : Monday, October 11, 2021 - 1:24:09 PM

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  • HAL Id : lirmm-00244002, version 1

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Nadine Azemard, Michel Aline, Daniel Auvergne. Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation. IWLS: International Workshop on Logic Synthesis, Jun 1999, Lake Tahoe, CA, United States. pp.198-201. ⟨lirmm-00244002⟩

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