Skip to Main content Skip to Navigation
Conference papers

Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation

Complete list of metadatas

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244002
Contributor : Nadine Azemard <>
Submitted on : Thursday, February 7, 2008 - 10:58:37 AM
Last modification on : Friday, September 13, 2019 - 11:33:15 AM

Identifiers

  • HAL Id : lirmm-00244002, version 1

Collections

Citation

Nadine Azemard, Michel Aline, Daniel Auvergne. Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation. IWLS: International Workshop on Logic Synthesis, Jun 1999, Lake Tahoe, CA, United States. pp.198-201. ⟨lirmm-00244002⟩

Share

Metrics

Record views

86