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Conference Papers Year : 1999

Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Abstract

This paper adresses the problem of satisfying delay/power constraints using a post layout iterative gate sizing. Path sizing procedure is defined with a realistic evaluation of gate delay and power and an accurate estimation of parasitic capacitances. This sizing protocol is validated on ISCAS'85 benchmarks, and implemented in a prototype for Performance Optimization by Path selection (POPS). The efficiency of this sizing heuristic is compared to an industrial optimization tool, AMPS (Synopsis).
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Dates and versions

lirmm-00244003 , version 1 (07-02-2008)

Identifiers

  • HAL Id : lirmm-00244003 , version 1

Cite

Nadine Azemard, Michel Aline, Daniel Auvergne. Satisfaction of Delay/Power Constraints by Iterative Gate Sizing. PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1999, Kos, Greece. pp.325-334. ⟨lirmm-00244003⟩
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