Structure Independent Representation of Output Transition Time for CMOS Library

Abstract : Non zero signal rise and fall times significantly contribute to the gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macro-model of the timing performance of CMOS structures, we present in this paper a general representation of transition times allowing fast and accurate cell performance evaluation. This general representation is then exploited to define a robust characterization protocol of the output transition time of standard cells. Both the representation and the protocol are finally validated comparing calculated gate input-output transition time values with standard look-up representation obtained from Hspice simulations (Bsim3v.3, level 69, 0.25Μm process).
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Communication dans un congrès
PATMOS'02: 12th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2002, Seville, Espagne, pp.247-257, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244012
Contributeur : Nadine Azemard <>
Soumis le : jeudi 7 février 2008 - 11:15:06
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00244012, version 1

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Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS'02: 12th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2002, Seville, Espagne, pp.247-257, 2002. 〈lirmm-00244012〉

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