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Structure Independent Representation of Output Transition Time for CMOS Library

Abstract : Non zero signal rise and fall times significantly contribute to the gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macro-model of the timing performance of CMOS structures, we present in this paper a general representation of transition times allowing fast and accurate cell performance evaluation. This general representation is then exploited to define a robust characterization protocol of the output transition time of standard cells. Both the representation and the protocol are finally validated comparing calculated gate input-output transition time values with standard look-up representation obtained from Hspice simulations (Bsim3v.3, level 69, 0.25Μm process).
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Submitted on : Friday, September 13, 2019 - 12:28:02 PM
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Philippe Maurine, Nadine Azemard, Daniel Auvergne. Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩. ⟨lirmm-00244012⟩



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