CMOS Gate Sizing under Delay Constraint

Abstract : In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25µm process by comparing the different constraint distribution techniques on various benchmarks.
Type de document :
Communication dans un congrès
PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.60-69, 2003
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244021
Contributeur : Nadine Azemard <>
Soumis le : jeudi 7 février 2008 - 11:24:00
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00244021, version 1

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Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azemard, Daniel Auvergne. CMOS Gate Sizing under Delay Constraint. PAMOS'03: 13th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2003, Torino, Italy, pp.60-69, 2003. 〈lirmm-00244021〉

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