CMOS Gate Sizing under Delay Constraint
Résumé
In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25µm process by comparing the different constraint distribution techniques on various benchmarks.
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