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Conference Papers Year : 2008

AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis

Abstract

Re-using embedded resources for implementing built-in self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement cost-efficient built-in self test functions from the AES cryptoalgorithm hardware implementation in a secure system. Self-test of the proposed implementation is also presented. A statistical test suite and fault-simulation are used for evaluating the efficiency of the corresponding cryptocore as pseudo-random test pattern generator; an analytical approach demonstrates the low probability of aliasing when used for test response compaction.
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Dates and versions

lirmm-00258769 , version 1 (25-02-2008)

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Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis. 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA), Jan 2008, Hong-Kong, China. pp.314-321, ⟨10.1109/DELTA.2008.86⟩. ⟨lirmm-00258769⟩
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