If we take a look at the latest ITRS 2001 edition[1], we will realize the number and difficulties of technical challenges the semiconductor industry must solve. Traditional scaling which has been at the basis of the semi conductor industry during these last three decades is indeed beginning to show limits in CMOS planar process as well as in connecting each elementary active device. The new edition roadmap highlight the need of modeling lithography technology, deposition and etch variation across a wafer, and simulating gate stack and ultra shallow dopant distributions, and junctions. Extensive studies are also required in high frequency circuit modeling. Efficient simulation of full chip interconnect delay is also needed as well as 3D transmission line interconnect simulation.