Initialization of Partially LBISTed Sequential Circuits

Abstract : Full scan is the most widely accepted and used DfT approach for large sequential machines. Nevertheless, in very dedicated cases it cannot be used mainly due to performance reasons as for example in high performance deeply pipelined CPU units. In this case full scan approach has to be replaced by partial scan. When trying to apply LogicBIST on partially scanned machines, the initialization problem of non-scan elements has to be solved. In this paper, we propose a nearly optimal algorithm to obtain a minimum set of memory elements to be initialized enabling to solve this initialization problem.
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Communication dans un congrès
ETW: European Test Workshop, May 2002, Corfou, Greece. 7th IEEE European Test Workshop, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269339
Contributeur : Christine Carvalho de Matos <>
Soumis le : samedi 21 janvier 2017 - 15:56:19
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : samedi 22 avril 2017 - 12:45:56

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  • HAL Id : lirmm-00269339, version 1

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Isabelle Vogel, Marie-Lise Flottes, Christian Landrault. Initialization of Partially LBISTed Sequential Circuits. ETW: European Test Workshop, May 2002, Corfou, Greece. 7th IEEE European Test Workshop, 2002. 〈lirmm-00269339〉

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