Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2003

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint

Abstract

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.
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Dates and versions

lirmm-00269529 , version 1 (20-01-2017)

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Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC: International Test Conference, Sep 2003, Charlotte, United States. pp.488-493, ⟨10.1109/TEST.2003.1270874⟩. ⟨lirmm-00269529⟩
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