Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint

Abstract : Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.
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Communication dans un congrès
ITC: International Test Conference, Sep 2003, Charlotte, United States. pp.488-493, 2003, 〈10.1109/TEST.2003.1270874〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269529
Contributeur : Christine Carvalho de Matos <>
Soumis le : vendredi 20 janvier 2017 - 18:28:01
Dernière modification le : jeudi 24 mai 2018 - 15:59:25
Document(s) archivé(s) le : vendredi 21 avril 2017 - 16:45:33

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Yannick Bonhomme, Patrick Girard, L. Guiller, Christian Landrault, Serge Pravossoudovitch. Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC: International Test Conference, Sep 2003, Charlotte, United States. pp.488-493, 2003, 〈10.1109/TEST.2003.1270874〉. 〈lirmm-00269529〉

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