Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs
Résumé
The objective of this paper is to analyze the detection of defects located in look-up-tables (LUTs) of SRAM-based FPGAs in the context of delay testing. Firstly, the static and dynamic behaviors of FPGA LUTs are described. Secondly, it is demonstrated that physical defects in FPGA LUTs can create delay faults. The detection of such delay faults is analyzed and requirements on test vectors are derived. Finally, an optimal test sequence, detecting all possible delay faults in a LUT, is defined in the context a manufacturing oriented test procedure (MOTP) as well as in the context of an application-oriented test procedure (AOTP).
Mots clés
integrated circuit testing
logic testing
AOTP
LUT dynamic behavior
LUT static behaviour
MOTP
SRAM-based FPGA
application-oriented test procedure
delay fault detection
delay testing
look-up tables
manufacturing oriented test procedure
physical defect detection
test sequence optimization
test vectors
Circuit faults
Circuit testing
Delay
Fault detection
Field programmable gate arrays
Integrated circuit interconnections
Logic arrays
Manufacturing
Programmable logic arrays
Table lookup