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Metric Definition for Circuit Speed Optimization

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269568
Contributor : Christine Carvalho de Matos <>
Submitted on : Thursday, April 3, 2008 - 8:21:50 AM
Last modification on : Wednesday, October 24, 2018 - 9:02:05 AM

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  • HAL Id : lirmm-00269568, version 1

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Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460. ⟨lirmm-00269568⟩

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