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Power Conscious Testing

Abstract : Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this paper, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269649
Contributor : Christine Carvalho de Matos <>
Submitted on : Friday, June 7, 2019 - 6:47:45 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Power Conscious Testing. EWDTC: East-West Design & Test Conference, Sep 2003, Yalta, Ukraine. pp.29-31. ⟨lirmm-00269649⟩

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