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Conference Papers Year : 2003

An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis

Abstract

Designers are today facing two challenges of conflicting objectives. In one hand they need to design for optimum performance and in the other hand they need to design in a minimum time frame ("time to market") while using the latest up-to-date available technology. It becomes necessary for the designers to very quickly prototype IP blocks for any given technology. This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors).
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Dates and versions

lirmm-00269694 , version 1 (20-07-2018)

Identifiers

  • HAL Id : lirmm-00269694 , version 1

Cite

Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, et al.. An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.266-271. ⟨lirmm-00269694⟩
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