An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis

Abstract : Designers are today facing two challenges of conflicting objectives. In one hand they need to design for optimum performance and in the other hand they need to design in a minimum time frame ("time to market") while using the latest up-to-date available technology. It becomes necessary for the designers to very quickly prototype IP blocks for any given technology. This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors).
Type de document :
Communication dans un congrès
DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. 18th International Conference on Design of Circuits and Integrated Systems, pp.266-271, 2003
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269694
Contributeur : Christine Carvalho de Matos <>
Soumis le : vendredi 20 juillet 2018 - 22:06:15
Dernière modification le : mardi 21 août 2018 - 20:00:04

Fichier

proceedings pages 284 - 289.pd...
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : lirmm-00269694, version 1

Collections

Citation

Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, et al.. An I.P. Migration and Prototyping Strategy Using Transistor Level Synthesis. DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. 18th International Conference on Design of Circuits and Integrated Systems, pp.266-271, 2003. 〈lirmm-00269694〉

Partager

Métriques

Consultations de la notice

175

Téléchargements de fichiers

5