SoC Symbolic Simulation: A Case Study on Delay Fault Testing - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2008

SoC Symbolic Simulation: A Case Study on Delay Fault Testing

Abstract

Functional test methodologies such as Software-Based Self-Test appear to suit well SoC delay fault testing. State-of-the-art solutions in this topic are quite far from maturity and few works consider Software-based Diagnosis for delay faults. In this paper we evaluate benefits and costs in using symbolic simulation for SoCs, in particular focusing on embedded processor core testing. Symbolic simulation principles are key to enable fast analysis and speed up delay fault diagnosis; to cope with SoC behavior, the traditional 6-valued symbolic algebra was expanded in order to tackle X and Z logic states. As a case study we consider a large design including many core types and suitable DFT for performing high quality test without scan chains.
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Dates and versions

lirmm-00278340 , version 1 (12-05-2008)

Identifiers

  • HAL Id : lirmm-00278340 , version 1

Cite

Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi. SoC Symbolic Simulation: A Case Study on Delay Fault Testing. DDECS'08: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2008, Bratislava, Slovakia. pp.320-325. ⟨lirmm-00278340⟩
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