Using TMR Architectures for Yield Improvement

Abstract : With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we use the classical Triple Modular Redundancy (TMR) fault tolerant architecture as a case study. Firstly we analyze the conditions that make the use of TMR architectures interesting for yield improvement purpose. In the second part of the paper, we investigate the test requirements for the TMR architecture and we propose a solution for generating test patterns for this type of architecture. Finally, we propose a new manner to implement the TMR architecture that makes it very effective for yield improvement purpose. Experimental results are provided on ISCAS and ITC benchmark circuits to prove the efficiency of the proposed approach in terms of yield improvement with a low area overhead.
Type de document :
Communication dans un congrès
DFT'08: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct 2008, pp.007-015, 2008, 〈www.dfts.org〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00326901
Contributeur : Alberto Bosio <>
Soumis le : lundi 6 octobre 2008 - 13:44:12
Dernière modification le : vendredi 2 mars 2018 - 19:36:02

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  • HAL Id : lirmm-00326901, version 1

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Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. Using TMR Architectures for Yield Improvement. DFT'08: 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct 2008, pp.007-015, 2008, 〈www.dfts.org〉. 〈lirmm-00326901〉

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