On Hardware Generation of Random Single Input Change Test

Abstract : The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated. Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.
Type de document :
Communication dans un congrès
ETW'01: European Test Workshop, pp.117-123, 2001
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00345801
Contributeur : Arnaud Virazel <>
Soumis le : mercredi 10 décembre 2008 - 09:30:04
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

Identifiants

  • HAL Id : lirmm-00345801, version 1

Collections

Citation

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. On Hardware Generation of Random Single Input Change Test. ETW'01: European Test Workshop, pp.117-123, 2001. 〈lirmm-00345801〉

Partager

Métriques

Consultations de la notice

61