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Conference Papers Year : 2008

A Reliable Architecture for Substitution Boxes in Integrated Cryptographic

Abstract

In this paper we propose an on-line self-test architecture for hardware implementations of Advanced Encryption Standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. Because Substitution boxes (S-Box) represent the largest hardware in this architecture, we focus on faults affecting these S-Boxes and propose a trade-off between hardware overhead and fault latency. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with respect to side-channel attacks based on power analysis.

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Dates and versions

lirmm-00363783 , version 1 (24-02-2009)

Identifiers

  • HAL Id : lirmm-00363783 , version 1

Cite

Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32. ⟨lirmm-00363783⟩
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