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A Reliable Architecture for Substitution Boxes in Integrated Cryptographic

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we propose an on-line self-test architecture for hardware implementations of Advanced Encryption Standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. Because Substitution boxes (S-Box) represent the largest hardware in this architecture, we focus on faults affecting these S-Boxes and propose a trade-off between hardware overhead and fault latency. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with respect to side-channel attacks based on power analysis.
Keywords : AES SBox On-Line BIST
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Contributor : Giorgio Di Natale <>
Submitted on : Tuesday, February 24, 2009 - 2:24:00 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Tuesday, June 8, 2010 - 7:14:22 PM


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  • HAL Id : lirmm-00363783, version 1



Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32. ⟨lirmm-00363783⟩



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