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A Flexible Modeling and Simulation Framework for Design Space Exploration

Abstract : Applications like 4G baseband modem require single-chip implementation to meet the integration and the power consumption requirements. These applications involve a high computation performance with real-time constraints, low power consumption and low cost. The concept of MPSoC is well suited to this problem. It makes it possible to adjust the architecture, by allocating the computational power where it is needed to fit the application needs. This often implies that the software has to be developed at the same time the platform is refined. Algorithm designers need accurate performance estimation to guide their decisions and system architects need to provide a design with enough calculation capacity and flexibility. Based on the methodology used for the design of the 4G FAUST chipset, this paper presents a modeling and simulation framework for Design Space Exploration (DSE) which enables a rapid evaluation of the application-to-platform adequation. The key element of this work is a simple and flexible way of modeling application and architecture. Our SystemC-based simulation environment can support a broad range of architecture components (ASIC, DSP, NoC, bus, shared or distributed memory, ...) and application features (control flow, data exchange, interrupts, data-dependent processing, dynamic reconfiguration). Application and architecture models are separated to allow independent design space exploration. The simulation basically executes the algorithms on the architecture and monitors dynamic behavior such as communication transfers, resource conflicts, starvation, dynamic reconfiguration, etc.
Mots-clés : MPSOC 3GPP/LTE DSE
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Contributor : Camille Jalier <>
Submitted on : Monday, March 30, 2009 - 2:24:15 PM
Last modification on : Thursday, June 11, 2020 - 5:04:06 PM
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Camille Jalier, Gilles Sassatelli, D. Lattard. A Flexible Modeling and Simulation Framework for Design Space Exploration. SOC'08: International Symposium on System-on-Chip, Nov 2008, Tampere, Finland, pp.001-004, ⟨10.1109/ISSOC.2008.4694863⟩. ⟨lirmm-00371764⟩



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