Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable e-FPGA In Processor Pipeline and as a Co-processor

Abstract : We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power at lower frequency helps fabrication of chip in LP (Low Power) process compared to GP (General Purpose) which helps to significantly reduce Static Power which has become a very crucial issue at and beyond 90 nm technologies. Use of reconfigurable accelerator raises the question of its programming complexity, HW/SW partitioning and silicon overhead. We will present that silicon overhead of eFPGA is small compared to the benefits which can be obtained with it. We will present a profiling tool which we created for our experiments. To analyze the issue of programming complexity we have explored state of the art Catapulttrade ESL tool of Mentor Graphicsreg.
Type de document :
Communication dans un congrès
DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.184-189, 2009, 〈10.1109/DATE.2009.5090655〉
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Contributeur : Martine Peridier <>
Soumis le : jeudi 2 avril 2009 - 15:32:04
Dernière modification le : mardi 26 juin 2018 - 01:18:36

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Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Julien Eydoux, Laurent Rougé. Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable e-FPGA In Processor Pipeline and as a Co-processor. DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.184-189, 2009, 〈10.1109/DATE.2009.5090655〉. 〈lirmm-00372842〉

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