Product On-Chip Process Compensation for Low Power and Yield Enhancement

Abstract : This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.
Type de document :
Communication dans un congrès
Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.247-255, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433504
Contributeur : Nadine Azemard <>
Soumis le : jeudi 19 novembre 2009 - 15:31:39
Dernière modification le : mercredi 17 octobre 2018 - 17:20:02

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  • HAL Id : lirmm-00433504, version 1

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Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. Product On-Chip Process Compensation for Low Power and Yield Enhancement. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.247-255, 2009. 〈lirmm-00433504〉

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