Skip to Main content Skip to Navigation
Conference papers

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Abstract : This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.
Complete list of metadatas

Cited literature [8 references]  Display  Hide  Download

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433504
Contributor : Nadine Azemard <>
Submitted on : Friday, September 13, 2019 - 11:39:44 AM
Last modification on : Friday, September 13, 2019 - 11:40:46 AM
Long-term archiving on: : Saturday, February 8, 2020 - 6:00:09 PM

File

ark__67375_HCB-FD0N7XWS-8.pdf
Publisher files allowed on an open archive

Identifiers

Collections

Citation

Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azemard, Vincent Dumettier, et al.. Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩. ⟨lirmm-00433504⟩

Share

Metrics

Record views

370

Files downloads

87