A Diagnosis Method for System-On-Chip

Abstract : This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed errors. The fault model allocation phase associates a set of fault models on each suspected line. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
Type de document :
Communication dans un congrès
Research in Microelectronics and Electronics 2009. PRIME'09. Ph. D., pp.276-279, 2006, 〈10.1109/RME.2009.5201373〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433762
Contributeur : Alberto Bosio <>
Soumis le : vendredi 20 novembre 2009 - 10:37:09
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Youssef Benabboud, Alberto Bosio, Olivia Riewer. A Diagnosis Method for System-On-Chip. Research in Microelectronics and Electronics 2009. PRIME'09. Ph. D., pp.276-279, 2006, 〈10.1109/RME.2009.5201373〉. 〈lirmm-00433762〉

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