A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2010

A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction

Abstract

Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered.
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Dates and versions

lirmm-00493204 , version 1 (18-06-2010)

Identifiers

  • HAL Id : lirmm-00493204 , version 1

Cite

Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction. ETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.81-86. ⟨lirmm-00493204⟩
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