Parallel Test of Identical Cores Using Test Elevators in 3D Circuits

Alberto Bosio 1 Giorgio Di Natale 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
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Poster communications
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00537857
Contributor : Martine Peridier <>
Submitted on : Friday, November 19, 2010 - 3:29:29 PM
Last modification on : Sunday, September 22, 2019 - 12:45:41 PM

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  • HAL Id : lirmm-00537857, version 1

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Alberto Bosio, Giorgio Di Natale. Parallel Test of Identical Cores Using Test Elevators in 3D Circuits. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Nov 2010, Austin, TX, United States. IEEE, 1st International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010. ⟨lirmm-00537857⟩

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