Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper proposes a novel method intended to accelerate the checking of the robustness of a device against Differential Power Analysis. We propose an algorithm for the automatic selection of shortest short input vector sequence that leads to the secret key breakthrough. We show that the selected sequence remains valid for different designs of the same cryptographic function.
keyword : DPA
Type de document :
Communication dans un congrès
DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261, 2010
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00539993
Contributeur : Giorgio Di Natale <>
Soumis le : jeudi 25 novembre 2010 - 17:06:38
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00539993, version 1

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261, 2010. 〈lirmm-00539993〉

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