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On using a SPICE-like TSTAC™ eFlash model for design and test

Abstract : The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00592203
Contributor : Martine Peridier <>
Submitted on : Wednesday, May 11, 2011 - 3:44:54 PM
Last modification on : Friday, August 30, 2019 - 10:46:56 AM

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Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS: Design and Diagnostics of Electronic Circuits ans Systems, Apr 2011, Cottbus, Germany. pp.359-370, ⟨10.1109/DDECS.2011.5783111⟩. ⟨lirmm-00592203⟩

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