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New Security Threats Against Chips Containing Scan Chain Structures

Jean da Rolt 1 Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Insertion of scan chains is the most common technique to ensure observability and controllability of sequential elements in an IC. However, when the chip deals with secret information, the scan chain can be used as back door for accessing secret (or hidden) information, and thus jeopardize the overall security. Several scan-based attacks on cryptographic functions have been described and showed the need for secure scan implementations. These attacks assume a single scan chain. However the conception of large designs and restrictions in terms of test costs may require the implementation of many scan chains and additional test infrastructures for test response compaction. In this paper, we present a new generic scan attack that covers a wide range of industrial test infrastructures, including spatial response compressors. Keywords: Security, Testability, Scan-based attack.
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Contributor : Martine Peridier <>
Submitted on : Friday, June 10, 2011 - 3:59:37 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Sunday, September 11, 2011 - 2:25:40 AM


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  • HAL Id : lirmm-00599690, version 1



Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. New Security Threats Against Chips Containing Scan Chain Structures. HOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110. ⟨lirmm-00599690⟩



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