Timing Issues for an Efficient Use of Concurrent Error Detection Codes
Résumé
This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed, and so timing conditions are suggested for a more efficient use of them.
Mots clés
- fault tolerance
- transient faults
- soft errors
- single soft error detection
- error detection codes
- logic circuits
- transients
- CED code-based scheme
- concurrent error detection code-based scheme
- logic circuit
- short-duration single transient fault
- security
- Circuit faults
- Clocks
- Fault tolerant systems
- Registers
- Timing
- Transient analysis
- concurrent error dectection codes
- fault attacks
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paperLATW-CEDtechniqueProblem-bastos-20110125bwa.pdf (413.56 Ko)
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