Timing Issues of Transient Faults in Concurrent Error Detection Schemes

Rodrigo Possamai Bastos 1, * Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
* Corresponding author
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in combinational logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed whether flip-flops are used to register the error signals, and so timing conditions are suggested for a more efficient use of them.
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Poster communications
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00701798
Contributor : Rodrigo Possamai Bastos <>
Submitted on : Saturday, May 26, 2012 - 4:10:31 PM
Last modification on : Thursday, February 7, 2019 - 4:02:32 PM
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Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/, 2011. ⟨lirmm-00701798⟩

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