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Conference Papers Year : 2011

Timing Issues of Transient Faults in Concurrent Error Detection Schemes

Abstract

This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in combinational logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed whether flip-flops are used to register the error signals, and so timing conditions are suggested for a more efficient use of them.
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Dates and versions

lirmm-00701798 , version 1 (26-05-2012)

Identifiers

  • HAL Id : lirmm-00701798 , version 1

Cite

Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Jun 2011, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/. ⟨lirmm-00701798⟩
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