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Advanced Test Methods for SRAMs

Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Serge Pravossoudovitch 1 Arnaud Virazel 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called 'static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as 'dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805049
Contributor : Luigi Dilillo <>
Submitted on : Tuesday, March 26, 2013 - 8:05:56 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Advanced Test Methods for SRAMs. VTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. pp.300-301, ⟨10.1109/VTS.2012.6231070⟩. ⟨lirmm-00805049⟩

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