Test Solution for Data Retention Faults in Low-Power SRAMs

Abstract : Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.
Type de document :
Communication dans un congrès
EDA Association. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition, pp.442-447, 2013, 〈http://www.date-conference.com/〉. 〈10.7873/DATE.2013.099〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805140
Contributeur : Luigi Dilillo <>
Soumis le : mercredi 27 mars 2013 - 10:56:47
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Test Solution for Data Retention Faults in Low-Power SRAMs. EDA Association. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition, pp.442-447, 2013, 〈http://www.date-conference.com/〉. 〈10.7873/DATE.2013.099〉. 〈lirmm-00805140〉

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