Test Solution for Data Retention Faults in Low-Power SRAMs - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2013

Test Solution for Data Retention Faults in Low-Power SRAMs


Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.


Fichier principal
Vignette du fichier
04.6_2.PDF (1 Mo) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

lirmm-00805140 , version 1 (06-03-2023)



Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Test Solution for Data Retention Faults in Low-Power SRAMs. DATE 2013 - 16th Design, Automation and Test in Europe Conference, Mar 2013, Grenoble, France. pp.442-447, ⟨10.7873/DATE.2013.099⟩. ⟨lirmm-00805140⟩
153 View
32 Download



Gmail Mastodon Facebook X LinkedIn More