Skip to Main content Skip to Navigation
Conference papers

Test Solution for Data Retention Faults in Low-Power SRAMs

Abstract : Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.
Document type :
Conference papers
Complete list of metadatas

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805140
Contributor : Luigi Dilillo <>
Submitted on : Wednesday, March 27, 2013 - 10:56:47 AM
Last modification on : Wednesday, December 11, 2019 - 1:32:02 AM

Identifiers

Collections

Citation

Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Test Solution for Data Retention Faults in Low-Power SRAMs. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. pp.442-447, ⟨10.7873/DATE.2013.099⟩. ⟨lirmm-00805140⟩

Share

Metrics

Record views

236