Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation
Résumé
Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulated-annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.
Mots clés
automatic test pattern generation
capacitors
delays
iterative methods
power supply circuits
simulated annealing
ITC'99 benchmarks
cell library characterization
close-form mathematical model
decoupling capacitor
gate level
ground bounce distribution
levelized simulation
nodal analysis formulation
path delay variation
physical design data
simulated-annealing-based iterative process
test pattern generation
uncorrelated power supply noise
worst case path delay
Delay
Integrated circuit modeling
Logic gates
Noise
Power supplies
Resonant frequency
Test pattern generators
Automatic test pattern generation (ATPG)
deep submicrometer
delay test
ground bounce
pattern selection
power supply noise
timing analysis
Origine : Fichiers éditeurs autorisés sur une archive ouverte
Loading...