Dynamic Energy Optimization in NoC-based System-on-Chips - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Low Power Electronics Year : 2010

Dynamic Energy Optimization in NoC-based System-on-Chips


Overall complexity of regular architectures is drastically increasing in nowadays System-on-Chip (SoC). Many cores are embedded in the same device and interconnected with a Network-on-Chip (NoC), providing more functionality with higher performance. The complexity of such systems introduces many challenges; one of them, probably the most important, is the power management. This paper focuses on the use of low-cost optimization mechanisms able to manage at run-time the SoC power consumption, when sequentially running applications with very different performance features, on chips with unequal characteristics due to technology variability. The optimization process is used to set the appropriate frequency of cores each time the application changes. This process has to meet some constraints. First of all, it operates intrusively on the fly to tackle changes in the system. Besides, fast response, low complexity and stability are required to have an efficient and reliable control scheme. The complexity of the optimization process has to scale with the number of cores. As a consequence, centralized optimization methods may present some drawbacks when the number of cores goes up to hundred. On the other side, distributed optimization methods can scale better, but may increase the total communications in the system. In this paper, we propose a distributed technique inspired by Game Theory (GT) to solve this optimization issue. In order to show the pertinence of the approach, we compare this solution to a centralized one based on state-of-the-art Lagrangian method. A telecom test-case application is used to compute the efficiency of the both techniques. Hardware/Software implementations of the game theoretic approach are proposed. We show that the optimization stage has an average latency of 5 ms and an area of 0.014 mm2 in 65 nm technology for the hardware implementation, which is really encouraging when considering SoC constraints.
No file

Dates and versions

lirmm-00818901 , version 1 (29-04-2013)



Imen Mansouri, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, et al.. Dynamic Energy Optimization in NoC-based System-on-Chips. Journal of Low Power Electronics, 2010, 6 (4), pp.564-577. ⟨10.1166/jolpe.2010.1106⟩. ⟨lirmm-00818901⟩
146 View
0 Download



Gmail Mastodon Facebook X LinkedIn More