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Power-Aware Testing and Test Strategies for Low Power Devices

Abstract : Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.
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Contributor : Patrick Girard <>
Submitted on : Monday, May 6, 2013 - 3:18:15 PM
Last modification on : Monday, November 30, 2020 - 9:30:04 AM
Long-term archiving on: : Monday, August 19, 2013 - 3:30:48 PM


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Patrick Girard, Nicola Nicolici, Xiaoqing Wen. Power-Aware Testing and Test Strategies for Low Power Devices. ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. Springer, 2012, 978-1-4419-0928-2. ⟨lirmm-00820737⟩



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