The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BLB) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.