Cellule mémoire volatile/non-volatile programmable

Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BLB) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.
Type de document :
Brevet
France, N° de brevet: FR 2970592 (B1) WO/2012/098184 (A1). 2013, pp.N/A
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00861512
Contributeur : Isabelle Gouat <>
Soumis le : jeudi 12 septembre 2013 - 18:57:39
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00861512, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Cellule mémoire volatile/non-volatile programmable. France, N° de brevet: FR 2970592 (B1) WO/2012/098184 (A1). 2013, pp.N/A. 〈lirmm-00861512〉

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