Cellule mémoire volatile/non-volatile compacte

Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (202), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (Rmin, Rmax), wherein said first storage node is coupled to a first access line (BL) via a third transistor (110, 810) connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor (112, 812) connected to said second storage node.
Type de document :
Brevet
France, N° de brevet: FR2970593 (B1) WO/2012/098197 (A1). 2013, pp.N/A
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00861513
Contributeur : Isabelle Gouat <>
Soumis le : jeudi 12 septembre 2013 - 19:07:07
Dernière modification le : jeudi 28 juin 2018 - 15:11:59

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  • HAL Id : lirmm-00861513, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Cellule mémoire volatile/non-volatile compacte. France, N° de brevet: FR2970593 (B1) WO/2012/098197 (A1). 2013, pp.N/A. 〈lirmm-00861513〉

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